The present invention relates to a semiconductor integrated circuit device, and to a technology effective for application to a semiconductor integrated circuit device equipped with a memory circuit.
It has been reported from the result of a known-example search subsequent to the completion or achievement of the invention of the present application that as ones related to such complementary bit-line precharge as described in the invention of the present application, there have been provided (1) gate boost precharge, (2) Unexamined Patent Publication No. 2000-100171 cited or listed below as a Patent Document 1, and (3) Unexamined Patent Publication No. Hei 10(1998)-178161 cited or listed below as a Patent Document 2. (1) is intended to boost the gate of a precharge MOS transistor to VPP (word line voltage) to thereby speed up a precharge operation for the purpose of speeding up of bit line precharge. (2) is intended to dispose only a short MOS transistor of a precharge circuit outside a shared MOS transistor to thereby speed up a precharge operation for the purpose of speeding up of bit line precharge. (3) aims to reduce a threshold voltage of a transistor of a precharge circuit to thereby speed up a precharge operation for the purpose of speeding up of bit line precharge.    Patent Document 1:            Unexamined Patent Publication No. 2000-100171            Patent Document 2:            Unexamined Patent Publication No. Hei 10(1998)-178161        